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    "topic": "Discussions ***unrelated*** to wafer.space or unconnected to IC design.\n\nPrefer <#1361349523724570941> for any IC design or wafer.space related chatter."
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      "timestamp": "2026-07-01T13:24:35.605+00:00",
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      "content": "Can i add custom chip art on the top and bottom right corner ( similar to the wafer space logo and qr in the left ) ? Or can i only add inside the pad ring ?",
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      "content": "yep, you can! I have a little image on the bottom right of mine. I think the top right may be reserved for an arrow this time around (to help the wirebonding alignment) so I think we can't use that corner",
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      "content": "Hey sure got it thank you much Will use only the bottom right",
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      "content": "You are also free to replace the wafer.space logo on the top left. The precheck only checks the bottom left and the top right, if you have CoB enabled.",
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      "content": "hah, I was skimming an old Adapteva parallela forum post looking for something and saw @tnt. Guess I shouldn't be surprised \uD83D\uDE42",
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      "content": "@BreakingTaps Good old times \uD83D\uDE05",
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      "content": "Chinese open source 55nm PDK? https://github.com/openecos-projects/icsprout55-pdk\n\n(Found via https://mp.weixin.qq.com/s/hDV_g7wtZvxg2IIAZ1XvGA)",
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      "content": "@BreakingTaps It was mentionned at FSiC last year but ... Not really open. If you look at it there is not much there. You get a standard cell library but only abstract view, no GDS. No DRC rules or any device simulation model.  So you can \"assemble\" a chip with purely digital design but nothing more, nothing custom, ...",
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      "content": "So you can do basically the same you can do with a FPGA.",
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      "content": "ah, welp",
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      "content": "maybe some day we'll get a 50-65nm open PDK",
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      "content": "haha that's amazing. i can't imagine making it DRC clean too \uD83D\uDE04",
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      "content": "Are you connected to ics55 in some way?",
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